An output circuit allowable to be built-in in an integrated circuit and which is available in the prior art and an input circuit allowable to be built-in in an integrated circuit and which is available in the prior art will be described below, referring to drawings.
Referring to FIGS. 1 and 2, an output circuit allowable to be built-in in an integrated circuit and which is available in the prior art has an open drain circuit consisting of an n channel normally on type field effect transistor (N101) connected a pull-up resister (R.sub.1) through a "PAD" of the IC in which the output circuit is built-in. The pull-up resister (R.sub.1) is arranged outside the IC and works under a power supply Vcc of e.g. 5V, despite the output circuit works under a power supply of e.g. 3V. The n channel normally on type field effect transistor (N101) has a function to reduce the voltage applied between the source and the drain of the n channel normally on type field effect transistor (N102). FIG. 2 shows that the voltage of the output signal very slowly increases up to the voltage of Vcc or 4V in this example, in excess of the voltage level of the voltage signal which is outputted from this output circuit and which is shown by (IN). It is noted that a very long time is required for transmission of a voltage signal having a potential level of e.g. 3V to an external circuit which works under a power supply of a higher voltage of e.g. 5V. Incidentally, it is noted the output circuit can be employed as the output circuit of an IC having a less amount of dielectric strength.
Referring to FIGS. 3 and 4, an input circuit allowable to be built-in in an integrated circuit and which is available in the prior art has an n channel normally on type field effect transistor (N100) which has a function to reduce the voltage of an input signal which is inputted through a "PAD" of the IC and which has a voltage range of zero through 5V to a voltage range ranging from zero to the voltage difference between the V.sub.DD voltage or the power supply voltage of circuit and the threshold voltage of the n channel normally on type field effect transistor (N100), before forwarding the input signal to the next stage circuit produced the IC. Therefore, the input circuit can be employed for an integrated circuit having a less amount of dielectric strength. The threshold voltage of the IC is designed to be less than that of the ordinary input circuit. In the drawing, "PAD" means the bonding pad for the input circuit. FIG. 4 shows the voltage of an input signal received at an input terminal (IN) is reduced to the potential level of the node (Y), before being applied to an amplifier and forwarded to the next stage circuit.
In the first place, referring to FIG. 2, the output signal outputted from the output circuit illustrated in FIG. 1 increases at a rate determined by a time constant which is further determined by the amount of the pull-up resister (R.sub.1). This means that if a high operation speed is required, a less amount of the pull-up resister (R.sub.1) is required. If the amount of the pull-up resister (R.sub.1) is made less, the power consumption increases accordingly, vice versa.
This is a drawback inevitably involved with the foregoing output circuit available in the prior art, described referring to FIGS. 1 and 2.
In the second place, supposing the power supply voltage of the input circuit illustrated in FIG. 3 or the V.sub.DD is 3V, an input signal of 5V inputted into the input circuit through the "PAD" is reduced to a value which is V.sub.DD less the threshold voltage of the n channel normally on type field effect transistor (N100), (V.sub.DD -V.sub.th) or approximately 2.3V, before being applied to the node (Y). Accordingly, it is not easy for such an input circuit to satisfy the requirement of VIH, which is a regulation inspecting whether or not an "H" level voltage issued by an input circuit has a sufficient amount of margin with respect to the threshold value of the internal circuit of the input circuit.
This is a drawback inevitably involved with the foregoing input circuit available in the prior art, described referring to FIGS. 3 and 4.